1. Field of the Invention
This invention relates to the field of optical architectures for generating high speed multi-GHz digital data for digital testing of GHz-type electronic or optical digital circuits using low-speed test vectors.
2. Description of the Prior Art
The objective of digital testing is to determine whether for a given input signal (usually called "input test vector" since it is a set of parallel input bits) the output value (or state) of the device under test (DUT) is in error for any of its output channels. State-of-the-art commercially available digital testers can test silicon based integrated circuits at speeds of the order of 200 MHz. Digital testing at 1-2 GHz rates as required for LSI GaAs integrated circuits or high-speed superconductive devices, is impossible with any known technology. This is because of the lack of an established high-speed technology that is capable of satisfying some rather stringent test requirements which include producing the required 1.5 GHz input test vectors, applying the input test vectors to the DUT while avoiding transmission line effects on the input signals, and accurately capturing and storing the output data of the DUT. Some of the specifications of a 1.5 GHZ (RZ) tester are 330 psec pulsewidth, rise/fall times of 50 psec, 35 psec edge resolution, and less than 65 psec system time skew.
In a general high-speed testing scenario, the input test vectors are produced via software and are stored in a slow speed parallel memory. The output channels of the parallel memory are read out in parallel and subsequently time-multiplexed (MUX), thus producing a high-speed serial waveform which is then applied to the DUT.
Presently, electrical techniques are used for generating and transferring the input test vectors to the DUT. These electrical techniques are unable to generate ultrashort psec-type pulses, implement high-speed multichannel time-multiplex devices, or provide the necessary high-speed DUT-tester interconnections. Consequently, there is a need for an apparatus and method for generating and transferring such high-speed digital test vectors to a digital device under test.